1. Field of the Invention
The present invention relates to bipolar transistors and, more particularly, to a bipolar transistor and a method of forming the bipolar transistor with a backside contact.
2. Description of the Related Art
A bipolar transistor is a well-known semiconductor device that is commonly used in integrated circuits. Structurally, a bipolar transistor has three regions, which include an emitter region, a base region, and a collector region. The emitter, base, and collector regions have alternating conductivity types with either an npn or a pnp sequence. One common method of fabricating a bipolar transistor is to vertically arrange the alternating conductivity types.
FIGS. 1A-1Q show a series of cross-sectional views that illustrate a prior-art method of fabricating vertically-arranged npn and pnp bipolar transistors. As shown in FIG. 1A, the method, which utilizes a p− semiconductor wafer 110, begins by implanting the top surface of p− semiconductor wafer 110 to form an n+ buried layer 114 in the top surface of p-type semiconductor wafer 110. N+ buried layer 114 can be formed with multiple implant energies to form a thick buried layer.
After n+ buried layer 114 has been formed, as further shown in FIG. 1A, a mask 115 is formed and patterned on the top surface of semiconductor wafer 110. Following this, the exposed regions of the top surface of p− semiconductor wafer 110 are implanted to form a p+ buried layer 116 in the top surface of n+ buried layer 114. As a result, p+ buried layer 116 is separated from p-type semiconductor wafer 110 by n+ buried layer 114. Once p+ buried layer 116 has been formed, mask 115 is removed.
After mask 115 has been removed, as shown in FIG. 1B, an epitaxial layer 120 is grown on the top surface of p-type semiconductor wafer 110. Next, a mask 122 is formed and patterned on the top surface of epitaxial layer 120. Following this, the exposed regions of epitaxial layer 120 are implanted to form a p− region 120P within epitaxial layer 120. Epitaxial layer 120 is formed to have an n-type conductivity and an n− dopant concentration. As a result, the formation of p− region 120P also defines an n− region 120N within epitaxial layer 120. After the implant, mask 122 is removed.
As shown in FIG. 1C, following the removal of mask 122, a number of deep trench isolation regions 124 and shallow trench isolation regions 126 are conventionally formed in epitaxial layer 120. The deep trench isolation regions 124 extend down below buried layer 114 to laterally isolate adjacent n+ buried layers 114.
As shown in FIG. 1D, once the trench isolation regions 124 and 126 have been formed, a mask 130 is formed and patterned on the top surface of epitaxial layer 120. Following this, the exposed regions of epitaxial layer 120 are implanted to form a p− base region 132 within n− region 120N of epitaxial layer 120. Mask 130 is then removed.
Next, a mask (not shown) is formed and patterned on the top surface of epitaxial layer 120. Following this, the exposed regions of epitaxial layer 120 are implanted to form an n− base region 134 within p− region 120P of epitaxial layer 120. Once n− base region 134 has been formed within p− region 120P, the mask is removed.
After this, as shown in FIG. 1E, a mask 136 is formed and patterned on the top surface of epitaxial layer 120. Following this, the exposed regions of epitaxial layer 120 are implanted to form an n+ sinker region 140 within n− region 120N of epitaxial layer 120. Once n+ sinker region 140 has been formed, mask 136 is removed. N+ buried layer 114, n− region 120N, and n+ sinker region 140 function as the collector of the npn transistor.
Next, a mask (not shown) is formed and patterned on the top surface of epitaxial layer 120. Following this, the exposed regions of epitaxial layer 120 are implanted to form a p+ sinker region 142 within p− region 120P of epitaxial layer 120. Once p+ sinker region 142 has been formed within p− region 120P, the mask is removed. P+ buried layer 116, p− region 120P, and p+ sinker region 142 function as the collector of the pnp transistor.
The emitter regions and the base/emitter contact structures can be formed in a number of ways. For example, in a first process, as shown in FIG. 1F, once mask 136 has been removed, a mask 144 is formed and patterned on the top surface of epitaxial layer 120. Following this, the exposed regions of epitaxial layer 120 are implanted to form a p+ base contact region 150 in p− base region 132, and a p+ emitter 152 in n− base region 134. Mask 144 is then removed.
Next, as shown in FIG. 1G, a mask 154 is formed and patterned on the top surface of epitaxial layer 120. After mask 154 has been formed and patterned, the exposed regions of epitaxial layer 120 are implanted to form an n+ emitter region 156 in p− base region 132, and an n+ base contact region 158 in n− base region 134. Mask 154 is removed.
Once mask 154 has been removed, as shown in FIG. 1H, an isolation layer 160 is formed over the top of epitaxial layer 120. After this, a number of contacts 162 are conventionally formed to extend through isolation layer 160 to make electrical connections with n+ sinker region 140, p+ sinker region 142, p+ base contact region 150, p+ emitter region 152, n+ emitter region 156, and n+ base contact region 158.
As shown in FIG. 1I, after the emitter regions and the base/emitter contact structures have been formed, the method next forms an interconnect structure 164 using conventional fabrication processes. Interconnect structure 164 includes an insulation region 164-I that contacts isolation layer 160, a number of metal-1 traces 164-M1 that are connected to the contacts 162, a number of metal-2 traces 164-M2, a number of metal pads 164-P, and a number of metal vias 164-V that connect the metal-1 traces 164-M1 and the metal-2 164-M2 traces together, and the metal-2 traces 164-M2 and the pads 164-P together. (Only two metal layers are shown for purposes of clarity. Additional metal layers can also be used.)
The formation of interconnect structure 164 completes the wafer fabrication sequence, which produces vertically-arranged npn and pnp bipolar transistors. The npn transistor has n+ emitter region 156 that lies over a portion of p− base region 132 which, in turn, lies over n− region 120N and n+ buried layer 114. The pnp transistor has p+ emitter region 152 that lies over a portion of n− base region 134 which, in turn, lies over p− region 120P and p+ buried layer 116.
In a second process of forming the emitter regions and the emitter/base contact structures, as shown in FIG. 1J, once the n+ and p+ sinker regions 140 and 142 have been formed, a layer of first poly (poly1) 166 is deposited on the top surface of epitaxial layer 120. Next, a mask 168 is formed and patterned on the top surface of poly1 layer 166. Following this, the exposed regions of poly1 layer 166 are implanted to form a p+ region 166P in poly layer 166. After p+ region 166P has been formed, mask 168 is removed.
Next, a mask (not shown), which protects p+ region 166P, is formed and patterned on the top surface of poly1 layer 166. Following this, the exposed regions of poly1 layer 166 are implanted to form an n+ region 166N in poly1 layer 166. Once n+ region 166N has been formed in poly1 layer 166, the mask is removed.
After the mask has been removed, as shown in FIG. 1K, a non-conductive layer 170 is formed on the p+ and n+ regions 166P and 166N of poly1 layer 166. A mask 172 is then formed and patterned on non-conductive layer 170. Following this, as shown in FIG. 1L, the exposed regions of non-conductive layer 170 and poly1 layer 166 are etched to form a base contact structure 174 that includes a p+ poly1 region 174P with an overlying non-conductive cap 174C, a base contact structure 176 that includes a p+ poly1 region 176P with an overlying non-conductive cap 176C, a base contact structure 178 that includes an n+ poly1 region 178P with an overlying non-conductive cap 178C, and a base contact structure 180 that includes an n+ poly1 region 180P with an overlying non-conductive cap 180C. Mask 172 is then removed.
Once mask 172 has been removed, as shown in FIG. 1M, an isolation layer is deposited and then anisotropically etched back to form isolation spacers 182. Once isolation spacers 182 have been formed, a layer of second poly (poly2) 184 is deposited on non-conductive caps 174C, 176C, 178C, and 180C and isolation spacers 182. Next, a mask 186 is formed and patterned on the top surface of poly2 layer 184. Following this, the exposed regions of poly2 layer 184 are implanted to form an n+ region 184N in poly2 layer 184. After n+ region 184N has been formed, mask 186 is removed.
Next, a mask (not shown), which protects n+ region 184N, is formed and patterned on the top surface of poly2 layer 184. Following this, the exposed regions of poly2 layer 184 are implanted to form a p+ region 184P in poly2 layer 184. Once p+ region 184P has been formed in poly2 layer 184, the mask is removed.
As shown in FIG. 1N, after n+ and p+ regions 184N and 184P have been formed in poly2 layer 184, a mask 190 is formed and patterned on the top surface of poly2 layer 184. Following this, as shown in FIG. 1O, the exposed regions of poly2 layer 184 are etched to form an n+ emitter contact structure 192 and a p+ emitter contact structure 194. Mask 190 is then removed.
Semiconductor wafer 110 is then annealed which, in turn, causes dopants from the p+ poly1 regions 174P and 176P, n+ emitter contact structure 192, the n+ poly1 regions 178P and 180P, and p+ emitter contact structure 194 to outdiffuse. The outdiffusion from the p+ poly1 regions 174P and 176P forms p+ base contact regions 174A and 176A, respectively, in p− base region 132. The outdiffusion from n+ emitter contact structure 192 forms n+ emitter region 192A in p− base region 132. The outdiffusion from n+ poly1 regions 178P and 180P forms n+ base contact regions 178A and 180A in n− base region 134. The outdiffusion from p+ emitter contact structure 194 forms p+ emitter region 194A in n− base region 134.
After this, as shown in FIG. 1P, an isolation layer 196 is formed over the top of epitaxial layer 120. After this, a number of contacts 198 are conventionally formed to extend through isolation layer 196 to make electrical connections with n+ emitter contact structure 192, n+ sinker region 140, p+ emitter contact structure 194, and p+ sinker region 142; through both isolation layer 196 and isolation caps 174C and 176C to contact the p+ poly1 regions 174P and 176P; and through both isolation layer 196 and isolation caps 178C and 180C to contact the n+ poly1 regions 178P and 180P.
As shown in FIG. 1Q, the method next forms interconnect structure 164 shown in FIG. 1I using conventional fabrication processes. Interconnect structure 164 includes insulation region 164-I that contacts isolation layer 196, metal-1 traces 164-M1 that are connected to the contacts 198, metal-2 traces 164-M2, metal pads 164-P, and metal vias 164-V that connect the metal-1 traces 164-M1 and the metal-2 164-M2 traces together, and the metal-2 traces 164-M2 and the pads 164-P together.
The formation of interconnect structure 164 completes the wafer fabrication sequence, which produces vertically-arranged npn and pnp bipolar transistors. The npn transistor has n+ emitter region 192A that lies over a portion of p− base region 132 which, in turn, lies over n− region 120N and n+ buried layer 114. The pnp transistor has p+ emitter region 194A that lies over a portion of n− base region 134 which, in turn, lies over p− region 120P and p+ buried layer 116.
Although the above method forms vertically-arranged npn and pnp bipolar transistors, there is a need for alternate methods of forming bipolar transistors.